1. Technical Field of the Invention
The present invention relates to a process for realizing a fin field effect transistor (finFET), as well as to a transistor of the type obtained by such a process.
2. Description of Related Art
Many integrated circuits have been created experimentally which incorporate one or more finFET field effect transistors. Such a transistor comprises a channel which is oriented to conduct an electrical current parallel to the surface of a substrate of the circuit, and which has a section elongated perpendicularly to this substrate surface. Such a field effect transistor structure is suitable for forming a gate which is placed on both of the large sides of the channel, to provide control of the conductive state of the transistor. It is also suitable for manufacturing a multi-channel transistor in which neighboring channels are separated by an intermediate gate portion.
A finFET transistor is created from at least one thin portion (“fin”) of semiconductor material which is used to form the channel of the transistor, and possibly also its source and drain zones. This fin is defined by a mask which is formed on the monocrystalline silicon substrate at the position of said fin. The substrate material is then directionally etched where there is no mask, to a determined depth which is greater than that of the mask, such that the fin remains under the mask and is composed of the initial material of the substrate.
The fin of semiconductor material which is thus obtained, and which comprises the channel of the final transistor, is not electrically insulated from the active portion of the circuit substrate, which itself is also of crystalline semiconductor material. Three types of leakage current result. A first type of leakage current can circulate between the source and drain zones of the finFET transistor, via the active portion of the substrate situated below the channel. This first leakage current, internal to each transistor, is not controlled by its gate. In addition, the channel of the finFET transistor is also in electrical contact with the channels of other transistors of the same type via the substrate, which produces a second type of leakage current flowing between different transistors, i.e. inter-transistor leakage currents. A third type of leakage current may also appear between the channel of each finFET transistor and a lower part of the substrate when said part is connected to a reference potential terminal.
To avoid these leakage currents, it is known to realize the finFET transistor on an integrated circuit substrate which is of the SOI (Silicon on Insulator) type. Such a substrate comprises, in a lower part, an intermediate layer of electrically insulating material which is topped by a crystalline silicon layer. U.S. Pat. No. 6,645,797 discloses such a process for realizing a finFET transistor from an SOI substrate. The transistor which is obtained is electrically insulated from the lower part of the substrate by the intermediate layer of insulating material. However, the use of an SOI substrate increases the manufacturing cost of the integrated circuit.
It is also known to realize an electrical junction in proximity to the contact surface between the active portion of the substrate and the fin of the channel. Such an electrical junction, when it is reverse polarized, electrically insulates the channel of the transistor from the active portion of the substrate.
In a first method commonly used to realize such an electrical junction, the fin is first obtained and electrically doped by a first type of doping. Doping particles of a second type which are the opposite of the first doping type are then implanted in a lower part of the fin, using an oblique beam for the implantation which is oblique to the base of the fin, starting from each side. Implantation of doping particles in the middle and upper parts of the fin must be avoided, to conserve the electrical efficiency of the first doping in these parts destined to be used to form the transistor channel. In spite of operative precautions, however, doping particles of the second doping type are also unintentionally implanted in the channel. These then cause a reduction in the mobility of the channel carriers, as well as unintentional variations in the effective concentration of these carriers. The electrical conduction properties of finFET transistors realized in this manner under identical operating parameters therefore vary in an uncontrolled manner, leading to a low reproducibility of the electronic circuits obtained.
In a second method, the fin is still obtained and electrically doped in a first step, while covered by a mask. Doping particles of type opposite those doping the fin are then implanted in the substrate, except for the area of the substrate surface which is occupied by the fin and covered by the mask. The particles doping the substrate are implanted using a directional beam perpendicular to the substrate surface, to avoid the penetration of some of these particles into the fin through its lateral sides which are perpendicular to the substrate surface. An electrical junction then appears in the active part of the substrate, below the fin, due to a lateral diffusion of the doping particles parallel to the substrate surface, below the fin.
This second method presents the following disadvantages. Firstly, the properties of the electrical junction which is thus obtained are highly dependent on the width of the fin. This width is not always controlled with sufficient accuracy, however. The electrical insulation of the transistor channel then presents uncontrolled fluctuations between finFET transistors realized under identical operating parameters. In addition, because of a residual divergence of the beam which implants the doping particles in the active portion of the substrate, and/or because of an unintentional slope in the lateral sides of the fin, doping particles intended for the active portion of the substrate are also implanted in the fin. There are still unintentional variations in the mobility and concentration of the channel carriers.
In addition, in the two known methods described above, the unintentional implantation of doping particles, intended for the active portion of the substrate, into the lateral sides of the fin causes faceting of these sides. Such faceting prevents from obtaining an interface between the channel and the insulating gate layer of the finFET transistor which is slightly rough.
A need exists in the art for realizing a finFET transistor in a manner which does not have the disadvantages described above. In particular, a need exists in the art for realizing a finFET transistor which is compatible with the use of a bulk substrate for integrated circuits, resulting in a transistor which is electrically insulated from the substrate.